;buildInfoPackage: chisel3, version: 3.1.3, scalaVersion: 2.11.12, sbtVersion: 1.1.1, builtAtString: 2018-09-12 19:37:29.007, builtAtMillis: 1536781049007
circuit Hello : 
  module Hello : 
    input clock : Clock
    input reset : UInt<1>
    output io : {led : UInt<1>}
    
    reg cntReg : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[Hello.scala 24:23]
    reg blkReg : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Hello.scala 25:23]
    node _T_12 = add(cntReg, UInt<1>("h01")) @[Hello.scala 27:20]
    node _T_13 = tail(_T_12, 1) @[Hello.scala 27:20]
    cntReg <= _T_13 @[Hello.scala 27:10]
    node _T_14 = eq(cntReg, UInt<25>("h017d783f")) @[Hello.scala 28:15]
    when _T_14 : @[Hello.scala 28:28]
      cntReg <= UInt<1>("h00") @[Hello.scala 29:12]
      node _T_16 = not(blkReg) @[Hello.scala 30:15]
      blkReg <= _T_16 @[Hello.scala 30:12]
      skip @[Hello.scala 28:28]
    io.led <= blkReg @[Hello.scala 32:10]
    
